(1) Field of the Invention
The present invention relates to a program conversion apparatus which converts a source program into a machine-language sequence, and relates to a processor which executes the machine-language sequence output from the program conversion apparatus.
(2) Description of Related Art
A program conversion apparatus has a table showing relationships between (a) instructions written in a programming language such as a high-level language and an assembly language and (b) machine-language instructions. When a source program is input to the program conversion apparatus, the program conversion apparatus converts the source program into machine-language instruction sequences using the table.
A processor stores the machine-language instruction sequences in a ROM, reads out the machine-language instruction sequences sequentially in units of machine-language instructions from the ROM to an instruction register, decodes the instructions, and allow the components such as an ALU and a register to operate in accordance with the decoding results.
Buses contained in the processor are each composed of a plurality of signal lines. Power is consumed when a bit value passing through a signal line changes from 0 to 1 or from 1 to 0. Each signal line corresponds to one digit of the machine-language instructions. That means the more bit changes are included in the machine-language instruction sequences, the more power is consumed, where the bit change is a change between successive values in the same digit between two successive machine-language instructions. Accordingly, there has been a desire to reduce the number of bit changes in the machine-language instruction sequences to reduce the power consumption.
It is therefore an object of the present invention to provide a program conversion apparatus which converts a source program into machine-language instruction sequences having reduced number of bit changes, where the bit change is a change between values in the same digit between two successive machine-language instructions, a record medium recording a program for achieving the conversion, a processor for executing the converted machine-language instruction sequences, and a record medium recording a program for achieving the execution.
The above object is fulfilled by a program conversion apparatus for converting a source program into machine-language instructions to be executed by a processor, the processor reading out the machine-language instructions sequentially from a memory unit via a bus, the program conversion apparatus comprising:
a program storage means for storing the source program which includes a plurality of instructions, each instruction including one or more types of components; a machine-language storage means for storing a plurality of sets of two or more types of machine-language codes which correspond to a plurality of components of a predetermined type included in the plurality of instructions, the two or more types of machine-language codes in each set having different bit patterns; and a conversion means for converting the plurality of instructions stored in the program storage means into the machine-language instructions, wherein the conversion means converts each of the plurality of predetermined-type components selectively into one of the two or more types of machine-language codes so that changes in logical states of signal lines composing the bus are fewest for the machine-language instructions.
With the above construction, the program conversion apparatus converts a source program into machine-language instruction sequences that render the power consumption of a processor small. The machine-language instruction sequences have reduced number of bit changes, where the bit change is a change between values in the same digit between two successive machine-language instructions. This enables the processor to execute the machine-language instructions with less power consumption since when these instructions pass through the bus between the ROM and the instruction register bus, less power is consumed due to less bit changes (power consumption) in each signal line constituting the bus.
In the above program conversion apparatus, each of the plurality of predetermined-type components may indicate an operation, the machine-language storage means stores a plurality of sets of two types of operation codes corresponding to the plurality of predetermined-type components indicating operations, the two types of operation codes in each set having different bit patterns, and the conversion means converts each of the plurality of predetermined-type components selectively into one of the two types of operation codes so that changes in logical states of signal lines composing the bus are fewest for the machine-language instructions.
With the above construction, the program conversion apparatus converts a source program into machine-language instruction sequences that render the power consumption of a processor small. The machine-language instruction sequences have reduced number of bit changes in terms of the operation codes. This enables the processor to execute the machine-language instructions with less power consumption since when these instructions pass through the bus between the ROM and the instruction register bus, less power is consumed due to less bit changes (power consumption) in each signal line constituting the bus.
In the above program conversion apparatus, each digit of the machine-language instructions may correspond to one of the signal lines, the conversion means converts the plurality of instructions included in the source program one by one, and includes: a reading means for reading out the plurality of sets of two types of operation codes corresponding to the plurality of predetermined-type components; a calculation means for comparing, for each of the two types of operation codes in a set read by the reading means, a bit pattern of the operation code with bits in a corresponding position in an immediately preceding machine language instruction and calculating a number of bits in the bit pattern having different values from the immediately preceding machine language instruction; a judging means for judging which of the two types of operation code has a bit pattern with a lower number of different bit values; and a selecting means for selecting an operation code judged to have the bit pattern with the lower number of different bit values.
With the above construction, the program conversion apparatus converts a plurality of certain components of a source program into operation codes having short Hamming distances from the preceding operation codes, sequentially starting from the first component of the program. As a result, the machine-language instruction sequences converted from the source program have less bit changes in terms of the operation codes. This enables the processor to execute the machine-language instructions with less power consumption for the same reason stated earlier. It should be noted here that the Hamming distance is the sum of bit changes between two bit patterns having the same length, the bit change being a change between two values in the same digit. For example, between bit patterns xe2x80x9c10011xe2x80x9d and xe2x80x9c10110xe2x80x9d, there are bit changes in the third and fifth digits from left. In this case, the Hamming distance is 2.
In the above program conversion apparatus, the calculation means may include: an exclusive OR means for performing an exclusive OR for each digit between each of the two types of operation code in a set read by the reading means and the bits in the corresponding position in the immediately preceding machine language instruction; and an addition means for adding up each result of the exclusive OR means to obtain a sum for each of the two types of operation code, the sums being used as the number of bits in the bit pattern having different values from the immediately preceding machine language instruction.
With the above construction, it is possible to obtain the Hamming distance between two operation codes simply by calculating an exclusive OR for each digit in each of the two combinations of the operation codes and adding up the results for each code.
In the above program conversion apparatus, bit patterns that render the sum of the number of digit-value changes lower than a threshold value may be assigned to machine-language codes in the machine-language storage means that correspond to two predetermined components which have a high probability of being included in two successive instructions in the source program.
With the above construction, the number of digit-value changes in the entire machine-language instructions is reduced.
In the above program conversion apparatus, each digit of the machine-language instructions may correspond to one of the signal lines, the conversion means includes: a reading means for reading out the plurality of sets of two types of operation codes corresponding to the plurality of predetermined-type components from the machine-language storage means; a candidate generating means for generating a plurality of candidates which are different combinations of operation codes each of which is selected from each set of the two types of operation code; and a selection means for selecting one of the plurality of candidates that renders changes in values of the machine-language instructions passing through signal lines of the bus the smallest.
With the above construction, the conversion means can convert the source program into machine-language instructions having less digit-value changes by selecting one among a plurality of candidates.
In the above program conversion apparatus, the selection means may include: a calculation means for calculating the number of digit-value changes between each two successive operation codes in each of the plurality of candidates, and obtains a sum of the number of digit-value changes for each of the plurality of candidates; a judging means for judging which sum is the lowest; and a selection unit for selecting one of the plurality of candidates that corresponds to the sum judged by the judging means as the lowest.
With the above construction, the selection means can select one candidate that has the least number of digit-value changes by calculating the Hamming distance between each two successive operation codes and comparing the calculated Hamming distances.
In the above program conversion apparatus, each of the plurality of predetermined-type components may indicate a resource, the machine-language storage means stores a plurality of sets of two types of operand codes corresponding to the plurality of predetermined-type components indicating resources, the two types of operand codes in each set having different bit patterns, and the conversion means converts each of the plurality of predetermined-type components selectively into one of the two types of operand codes so that changes in logical states of signal lines composing the bus are fewest for the machine-language instructions.
With the above construction, the program conversion apparatus converts a source program into machine-language instruction sequences that render the power consumption of a processor small. The machine-language instruction sequences have reduced number of bit changes in terms of the operand codes. This enables the processor to execute the machine-language instructions with less power consumption since when these instructions pass through the bus between the ROM and the instruction register bus, less power is consumed due to less bit changes (power consumption) in each signal line constituting the bus.
In the above program conversion apparatus, each digit of the machine-language instructions may correspond to one of the signal lines, the conversion means converts the plurality of instructions included in the source program one by one, and includes: a reading means for reading out the plurality of sets of two types of operand codes corresponding to the plurality of predetermined-type components; a calculation means for comparing, for each of the two types of operand codes in a set read by the reading means, a bit pattern of the operand code with bits in a corresponding position in an immediately preceding machine language instruction and calculating a number of bits in the bit pattern having different values from the immediately preceding machine language instruction; a judging means for judging which of the two types of operand code has a bit pattern with a lower number of different bit values; and a selecting means for selecting an operand code judged to have the bit pattern with the lower number of different bit values.
With the above construction, the program conversion apparatus converts a plurality of certain components of a source program into operand codes having short Hamming distances from the preceding operand codes, sequentially starting from the first component of the program. As a result, the machine-language instruction sequences converted from the source program have less it changes in terms of the operand codes. This enables the processor to execute the machine-language instructions with less power consumption for the same reason stated earlier.
In the above program conversion apparatus, the calculation means may include: an exclusive OR means for performing an exclusive OR for each digit between each of the two types of operand code in a set read by the reading means and the bits in the corresponding position in the immediately preceding machine language instruction; and an addition means for adding up each result of the exclusive OR means to obtain a sum for each of the two types of operand code, the sums being used as the number of bits in the bit pattern having different values from the immediately preceding machine language instruction.
With the above construction, it is possible to obtain the Hamming distance between two operand codes simply by calculating an exclusive OR for each digit in each of the two combinations of the operand codes and adding up the results for each code.
In the above program conversion apparatus, each digit of the machine-language instructions may correspond to one of the signal lines, the conversion means includes: a reading means for reading out the plurality of sets of two types of operand codes corresponding to the plurality of predetermined-type components from the machine-language storage means; a candidate generating means for generating a plurality of candidates which are different combinations of operand codes each of which is selected from each set of the two types of operand code; and a selection means for selecting one of the plurality of candidates that renders changes in values of the machine-language instructions passing through signal lines of the bus the lowest.
With the above construction, the conversion means can convert the source program into machine-language instructions having less digit-value changes by selecting one among a plurality of candidates.
In the above program conversion apparatus, the selection means may include: a calculation means for calculating the number of digit-value changes between each two successive operand codes in each of the plurality of candidates, and obtains a sum of the number of digit-value changes for each of the plurality of candidates; a judging means for judging which sum is the lowest; and a selection unit for selecting one of the plurality of candidates that corresponds to the sum judged by the judging means as the lowest.
With the above construction, the selection means can select one candidate that has the least number of digit-value changes by calculating the Hamming distance between each two successive operand codes and comparing the calculated Hamming distances.
In the above program conversion apparatus, the conversion means may further include: a setting means for inserting an identification bit into each machine-language instruction converted by the conversion means, the identification bit indicating which of the two types of machine-language codes has been selected.
With the above construction, the processor that executes the machine-language instructions can identify the type of each instruction by referring to the identification bit.
The above object is also fulfilled by a program conversion apparatus for converting a source program into machine-language instructions to be executed by a processor, the processor reading out the machine-language instructions sequentially from a memory unit via a bus, the program conversion apparatus comprising: a program storage means for storing the source program which includes a plurality of instructions; a conversion means for converting the plurality of instructions stored in the program storage means into the machine-language instructions; and a replacing means for, every two times the conversion means outputs a machine-language instruction including both a source field and a destination field, replacing contents of the source field and the destination field with each other.
With the above construction, when two successive machine-language instructions are, for example, xe2x80x9cADD R1,R2xe2x80x9d (add up values stored in R1 and R2 and store the result into R2), and xe2x80x9cADD R2,R3xe2x80x9d (add up values stored in R2 and R3 and store the result into R3), the replacing means replaces R2 and R3 of the second instruction with each other to xe2x80x9cADD R3,R2xe2x80x9d. Alternatively, the replacing means replaces R1 and R2 of the first instruction with each other to xe2x80x9cADD R2,R1xe2x80x9d. After either of these replacements, R2 with the same bit pattern is placed at the same digit position in the two instructions, resulting in the Hamming distance 0 between the two instructions in terms of the R2 section.
In the above program conversion apparatus, the conversion means may convert the plurality of instructions into the machine-language instructions having a fixed length, and the replacing means replaces contents of the source field and the destination field with each other every two times the replacing means detects a machine-language instruction having a register number in at least one of the source field and the destination field.
With the above construction, the same effect as above can be obtained.
In the above program conversion apparatus, each machine-language instruction may have a bit field, and the replacing means inserts a bit value into the bit field of a machine-language instruction when the replacing means has replaced contents of the source field and the destination field of this machine-language instruction.
With the above construction, the processor that executes the machine-language instructions can determine whether the replacement has been performed by referring to the bit.
In the above program conversion apparatus, the replacing means may replace contents of the source field and the destination field with each other when an alternate machine-language instruction output from the conversion means has a register number in at least one of the source field and the destination field.
With the above construction, two successive machine-language instructions each have a section indicating a register placed at the same digit, resulting in the Hamming distance 0 at this section.
The above object is also fulfilled by a processor comprising: a reading means for reading a plurality of machine-language instructions sequentially from a memory via a bus, each of the plurality of machine-language instructions having either type-1 bit pattern or type-2 bit pattern, and has an identification bit which indicates either the type-1 bit pattern or the type-2 bit pattern; an identification means for identifying a bit pattern of each of the plurality of machine-language instructions read out by the reading means by referring to the identification bit; a first decoding means for decoding machine-language instructions having type-1 bit patterns and outputting decoding results; and a second decoding means for decoding machine-language instructions having type-2 bit patterns and outputting decoding results, wherein the first decoding means and the second decoding means output the same decoding result for the same machine-language instruction whether a bit patter thereof is type-1 or type-2.
With the above construction, the processor can execute the machine-language instructions that each have two bit patterns. By selectively combining the two bit patterns, the processor can execute the machine-language instructions with less power consumption since when these instructions pass through the bus between the ROM and the instruction register bus, less power is consumed due to less bit changes (power consumption) in each signal line constituting the bus.
In the above processor, the type-1 bit pattern and the type-2 bit pattern may be different from each other in terms of a bit pattern of an operation code included in each of the plurality of machine-language instructions, and the processor further comprises: an operand decoding unit for decoding operand codes of the plurality of machine-language instructions, wherein the first decoding means decodes operation codes of machine-language instructions having the type-1 bit pattern, and the second decoding means decodes operation codes of machine-language instructions having the type-2 bit pattern.
With the above construction, the processor can execute the machine-language instructions that each have two bit patterns in terms of the operation code section.
In the above processor, the type-1 bit pattern and the type-2 bit pattern may be different from each other in terms of a bit pattern of an operand code included in each of the plurality of machine-language instructions, each operand code corresponding to two different bit patterns and indicating the same register, and the processor further comprises: an operation decoding unit for decoding operation codes of the plurality of machine-language instructions, wherein the first decoding means decodes operand codes of machine-language instructions having the type-1 bit pattern, and the second decoding means decodes operand codes of machine-language instructions having the type-2 bit pattern.
With the above construction, the processor can execute the machine-language instructions that each have two bit patterns in terms of the operand code section.
In the above processor, each machine-language instruction may be classified into an order-1 type and an order-2 type regardless of a bit pattern thereof, the order-1 type indicating an order of a plurality of operand codes included in each machine-language instruction, and the order-2 type indicating another order of the plurality of operand codes, each machine-language instruction having a classification bit indicating the order-1 type or the order-2 type, and the operand decoding unit includes: a classification unit for classifying each machine-language instruction into the order-1 type or the order-2 type by referring to the classification bit; a rearranging unit for rearranging the plurality of operand codes of machine-language instructions of the order-2 type to the order-1 type; and a decoding unit for decoding operand codes of machine-language instructions of the order-1 type and operand codes rearranged by the rearranging unit from the order-2 type to the order-1 type.
With the above construction, the processor identifies the order type (order-1 type or order-2 type) of the operand codes by referring to the classification bit, and rearranges the operand codes of the order-2 type to the order-1 type to decode the machine-language instructions.
The above object is also fulfilled by a processor comprising: a reading means for reading a plurality of machine-language instructions sequentially from a memory via a bus, each of the plurality of machine-language instructions has a plurality of operands, and is classified into one of an order-1 type machine-language instruction and an order-2 type machine-language instruction, the order-1 type and order-2 type machine-language instructions having different orders of the plurality of operands; an identification means for identifying each of the plurality of machine-language instructions read out by the reading means as the order-1 type or the order-2 type machine-language instruction; a first decoding means for decoding order-1 type machine-language instructions and outputting decoding results; and a second decoding means for decoding order-2 type machine-language instructions and outputting decoding results.
With the above construction, when a machine-language instruction has, for example, a fixed length of 32 bits, the processor specifies the address of the next machine-language instruction by incrementing the program counter by four. In this case, the identification means can easily identify the type of each machine-language instruction by performing the simple judgement on whether the third bit from the least significant bit in the program counter is 0.
In the above processor, the second decoding means may include: a rearranging unit for rearranging orders of the plurality of operand codes of order-2 type machine-language instructions, decoding the rearranged operand codes, and outputting the same decoding results as the first decoding means.
With the above construction, the processor reads out each machine-language instruction with shorter Hamming distance from the ROM to the instruction register, and decodes it after restoring the order of the operands if the operands have been replaced with each other. This reduces the power consumption in the bus when such an instruction passes through the bus.